mSGDMA

2017.06.20.09:04:20 Datasheet
Overview
  clk  mSGDMA

All Components
   dispatcher_read modular_sgdma_dispatcher 17.0
   dispatcher_write modular_sgdma_dispatcher 17.0
   freq_counter_0 freq_counter 1.0
   mm_bridge_slv altera_avalon_mm_bridge 17.0
   prbs_pattern_checker prbs_pattern_checker 1.1
   prbs_pattern_generator prbs_pattern_generator 1.1
   timer_0 altera_avalon_timer 17.0
Memory Map
dma_read_master dma_write_master
 Data_Read_Master  Data_Write_Master
  dispatcher_read
CSR 
Descriptor_Slave 
  dispatcher_write
CSR 
Descriptor_Slave 
  freq_counter_0
csr 
  prbs_pattern_checker
csr 
  prbs_pattern_generator
csr 
  timer_0
s1 

clk

clock_source v17.0


Parameters

clockFrequency 75000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

dispatcher_read

modular_sgdma_dispatcher v17.0
mm_bridge_slv m0   dispatcher_read
  CSR
m0  
  Descriptor_Slave
dma_read_master Response_Source  
  Read_Response_Sink
clk clk  
  clock
clk_reset  
  clock_reset
Read_Command_Source   dma_read_master
  Command_Sink


Parameters

PREFETCHER_USE_CASE 0
MODE 1
GUI_RESPONSE_PORT 0
RESPONSE_PORT 2
DESCRIPTOR_INTERFACE 0
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
DATA_WIDTH 32
DATA_FIFO_DEPTH 32
MAX_BYTE 1024
TRANSFER_TYPE Aligned Accesses
BURST_ENABLE 0
MAX_BURST_COUNT 2
BURST_WRAPPING_SUPPORT 0
STRIDE_ENABLE 0
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 0
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

dispatcher_write

modular_sgdma_dispatcher v17.0
mm_bridge_slv m0   dispatcher_write
  CSR
m0  
  Descriptor_Slave
dma_write_master Response_Source  
  Write_Response_Sink
clk clk  
  clock
clk_reset  
  clock_reset
Write_Command_Source   dma_write_master
  Command_Sink


Parameters

PREFETCHER_USE_CASE 0
MODE 2
GUI_RESPONSE_PORT 2
RESPONSE_PORT 2
DESCRIPTOR_INTERFACE 0
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
DATA_WIDTH 32
DATA_FIFO_DEPTH 32
MAX_BYTE 1024
TRANSFER_TYPE Aligned Accesses
BURST_ENABLE 0
MAX_BURST_COUNT 2
BURST_WRAPPING_SUPPORT 0
STRIDE_ENABLE 0
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 2
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

dma_read_master

dma_read_master v17.0
dispatcher_read Read_Command_Source   dma_read_master
  Command_Sink
clk clk  
  Clock
clk_reset  
  Clock_reset
Data_Source   prbs_pattern_checker
  st_pattern_input
Response_Source   dispatcher_read
  Read_Response_Sink


Parameters

DATA_WIDTH 32
LENGTH_WIDTH 25
FIFO_DEPTH 1024
USE_FIX_ADDRESS_WIDTH 0
FIX_ADDRESS_WIDTH 32
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 8
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 1
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
CHANNEL_ENABLE 0
CHANNEL_WIDTH 8
BYTE_ENABLE_WIDTH 4
BYTE_ENABLE_WIDTH_LOG2 2
AUTO_ADDRESS_WIDTH 32
ADDRESS_WIDTH 32
FIFO_DEPTH_LOG2 10
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 4
NUMBER_OF_SYMBOLS_LOG2 2
MAX_BURST_COUNT_WIDTH 4
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 1
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 8
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

dma_write_master

dma_write_master v17.0
dispatcher_write Write_Command_Source   dma_write_master
  Command_Sink
timing_adapter out  
  Data_Sink
clk clk  
  Clock
clk_reset  
  Clock_reset
Response_Source   dispatcher_write
  Write_Response_Sink


Parameters

DATA_WIDTH 32
LENGTH_WIDTH 25
FIFO_DEPTH 1024
USE_FIX_ADDRESS_WIDTH 0
FIX_ADDRESS_WIDTH 32
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 8
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 1
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
BYTE_ENABLE_WIDTH 4
BYTE_ENABLE_WIDTH_LOG2 2
AUTO_ADDRESS_WIDTH 32
ADDRESS_WIDTH 32
FIFO_DEPTH_LOG2 10
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 4
NUMBER_OF_SYMBOLS_LOG2 2
MAX_BURST_COUNT_WIDTH 4
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 1
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 8
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
ACTUAL_BYTES_TRANSFERRED_WIDTH 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

freq_counter_0

freq_counter v1.0
mm_bridge_slv m0   freq_counter_0
  csr
clk clk  
  clock
clk  
  sample_clock
clk_reset  
  reset


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 13333
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mm_bridge_slv

altera_avalon_mm_bridge v17.0
clk clk   mm_bridge_slv
  clk
clk_reset  
  reset
m0   dispatcher_write
  CSR
m0  
  Descriptor_Slave
m0   dispatcher_read
  CSR
m0  
  Descriptor_Slave
m0   prbs_pattern_generator
  csr
m0   prbs_pattern_checker
  csr
m0   freq_counter_0
  csr
m0   timer_0
  s1


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 20
SYSINFO_ADDR_WIDTH 9
USE_AUTO_ADDRESS_WIDTH 1
AUTO_ADDRESS_WIDTH 9
HDL_ADDR_WIDTH 9
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 4
MAX_BURST_SIZE 8
MAX_PENDING_RESPONSES 16
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

prbs_pattern_checker

prbs_pattern_checker v1.1
mm_bridge_slv m0   prbs_pattern_checker
  csr
dma_read_master Data_Source  
  st_pattern_input
clk clk  
  clock
clk_reset  
  reset


Parameters

DATA_WIDTH 32
PRBS_WIDTH 16
AUTO_CLOCK_CLOCK_RATE 75000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

prbs_pattern_generator

prbs_pattern_generator v1.1
mm_bridge_slv m0   prbs_pattern_generator
  csr
clk clk  
  clock
clk_reset  
  reset
st_pattern_output   timing_adapter
  in


Parameters

DATA_WIDTH 32
PRBS_WIDTH 16
AUTO_CLOCK_CLOCK_RATE 75000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

timer_0

altera_avalon_timer v17.0
mm_bridge_slv m0   timer_0
  s1
clk clk  
  clk
clk_reset  
  reset


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 75000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 74999
mult 0.001
ticksPerSec 1000.0
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 75000000
LOAD_VALUE 74999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

timing_adapter

timing_adapter v17.0
prbs_pattern_generator st_pattern_output   timing_adapter
  in
clk clk  
  clk
clk_reset  
  reset
out   dma_write_master
  Data_Sink


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 8
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady true
outUseReady true
inReadyLatency 1
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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