de10_lite_qsys

2016.08.16.11:31:50 Datasheet
Overview
  clk_in  de10_lite_qsys
Processor
   nios2_gen2 Nios II 15.1
All Components
   SEG7 SEG7_IF 1.0
   alt_vip_vfr alt_vip_vfr 14.0
   arduino_pio altera_avalon_pio 15.1
   arduino_spi altera_avalon_spi 15.1
   g_sensor_i2c_scl altera_avalon_pio 15.1
   g_sensor_i2c_sda altera_avalon_pio 15.1
   g_sensor_int altera_avalon_pio 15.1
   jtag_uart altera_avalon_jtag_uart 15.1
   mm_clock_crossing_bridge_0 altera_avalon_mm_clock_crossing_bridge 15.1
   modular_adc altera_modular_adc 15.1
   nios2_gen2 altera_nios2_gen2 15.1
   onchip_memory altera_avalon_onchip_memory2 15.1
   pio_key altera_avalon_pio 15.1
   pio_led altera_avalon_pio 15.1
   pio_sw altera_avalon_pio 15.1
   sdram altera_avalon_new_sdram_controller 15.1
   sysid_qsys altera_avalon_sysid_qsys 15.1
   system_pll altpll 15.1
   tft_spi_dc altera_avalon_pio 15.1
   timer altera_avalon_timer 15.1
Memory Map
alt_vip_vfr nios2_gen2
 avalon_master  data_master  instruction_master
  SEG7
avalon_slave  0x08000020
  alt_vip_vfr
avalon_slave  0x09081200
  arduino_pio
s1  0x090812b0
  arduino_spi
spi_control_port  0x09081280
  g_sensor_i2c_scl
s1  0x08000060
  g_sensor_i2c_sda
s1  0x08000050
  g_sensor_int
s1  0x08000040
  jtag_uart
avalon_jtag_slave  0x090812d8
  modular_adc
sequencer_csr  0x090812d0
sample_store_csr  0x09081000
  nios2_gen2
debug_mem_slave  0x09080800 0x09080800
  onchip_memory
s1  0x09040000 0x09040000
  pio_key
s1  0x08000070
  pio_led
s1  0x08000090
  pio_sw
s1  0x08000080
  sdram
s1  0x04000000 0x04000000 0x04000000
  sysid_qsys
control_slave  0x080000a0
  system_pll
pll_slave  0x090812c0
  tft_spi_dc
s1  0x090812a0
  timer
s1  0x08000000

SEG7

SEG7_IF v1.0
mm_clock_crossing_bridge_0 m0   SEG7
  avalon_slave
system_pll c3  
  clock_sink
clk_in clk_reset  
  clock_sink_reset


Parameters

SEG7_NUM 6
ADDR_WIDTH 3
DEFAULT_ACTIVE 1
LOW_ACTIVE 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cpr_0

alt_vip_cpr v13.1
alt_vip_vfr avalon_streaming_source   alt_vip_cpr_0
  din0
system_pll c0  
  clock
clk_in clk_reset  
  reset
nios2_gen2 debug_reset_request  
  reset
dout0   alt_vip_itc
  din


Parameters

DIN0_SYMBOLS_PER_BEAT 4
DIN1_ENABLED 0
DIN1_SYMBOLS_PER_BEAT 0
DOUT0_SYMBOLS_PER_BEAT 3
DOUT1_ENABLED 0
DOUT1_SYMBOLS_PER_BEAT 0
AUTO_DEVICE_FAMILY MAX10FPGA
PARAMETERISATION <colourPatternRearrangerParams><CPR_NAME>Color Plane Sequencer</CPR_NAME><CPR_BPS>8</CPR_BPS><CPR_PORTS><INPUT_PORT><NAME>din0</NAME><STREAMING_DESCRIPTOR>[A:B:C:discard]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED></INPUT_PORT><INPUT_PORT><NAME>din1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED></INPUT_PORT><OUTPUT_PORT><NAME>dout0</NAME><STREAMING_DESCRIPTOR>[A:B:C]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT><OUTPUT_PORT><NAME>dout1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT></CPR_PORTS><CPR_INPUT_2_PIXELS>false</CPR_INPUT_2_PIXELS></colourPatternRearrangerParams>
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

alt_vip_itc

alt_vip_itc v14.0
alt_vip_cpr_0 dout0   alt_vip_itc
  din
system_pll c0  
  is_clk_rst
clk_in clk_reset  
  is_clk_rst_reset
nios2_gen2 debug_reset_request  
  is_clk_rst_reset


Parameters

FAMILY MAX10FPGA
NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
BPS 8
INTERLACED 0
H_ACTIVE_PIXELS 800
V_ACTIVE_LINES 600
ACCEPT_COLOURS_IN_SEQ 0
FIFO_DEPTH 800
CLOCKS_ARE_SAME 0
USE_CONTROL 0
NO_OF_MODES 1
THRESHOLD 799
STD_WIDTH 1
GENERATE_SYNC 0
USE_EMBEDDED_SYNCS 0
AP_LINE 0
V_BLANK 0
H_BLANK 0
H_SYNC_LENGTH 128
H_FRONT_PORCH 40
H_BACK_PORCH 88
V_SYNC_LENGTH 4
V_FRONT_PORCH 1
V_BACK_PORCH 23
F_RISING_EDGE 0
F_FALLING_EDGE 0
FIELD0_V_RISING_EDGE 0
FIELD0_V_BLANK 0
FIELD0_V_SYNC_LENGTH 0
FIELD0_V_FRONT_PORCH 0
FIELD0_V_BACK_PORCH 0
ANC_LINE 0
FIELD0_ANC_LINE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_vfr

alt_vip_vfr v14.0
nios2_gen2 data_master   alt_vip_vfr
  avalon_slave
irq  
  interrupt_sender
debug_reset_request  
  clock_master_reset
debug_reset_request  
  clock_reset_reset
system_pll c0  
  clock_master
c0  
  clock_reset
clk_in clk_reset  
  clock_master_reset
clk_reset  
  clock_reset_reset
avalon_master   sdram
  s1
avalon_streaming_source   alt_vip_cpr_0
  din0


Parameters

FAMILY MAX10FPGA
BITS_PER_PIXEL_PER_COLOR_PLANE 8
NUMBER_OF_CHANNELS_IN_PARALLEL 4
NUMBER_OF_CHANNELS_IN_SEQUENCE 1
MAX_IMAGE_WIDTH 800
MAX_IMAGE_HEIGHT 600
MEM_PORT_WIDTH 128
RMASTER_FIFO_DEPTH 1024
RMASTER_BURST_TARGET 16
CLOCKS_ARE_SEPARATE 1
AUTO_CLOCK_RESET_CLOCK_RATE 120000000
AUTO_CLOCK_MASTER_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

arduino_pio

altera_avalon_pio v15.1
nios2_gen2 data_master   arduino_pio
  s1
debug_reset_request  
  reset
system_pll c3  
  clk
clk_in clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 16
clockRate 10000000
derived_has_tri true
derived_has_out false
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 10000000
HAS_IN 0
HAS_OUT 0
HAS_TRI 1
IRQ_TYPE NONE
RESET_VALUE 0

arduino_spi

altera_avalon_spi v15.1
nios2_gen2 data_master   arduino_spi
  spi_control_port
debug_reset_request  
  reset
system_pll c3  
  clk
clk_in clk_reset  
  reset


Parameters

clockPhase 0
clockPolarity 0
dataWidth 8
disableAvalonFlowControl false
insertDelayBetweenSlaveSelectAndSClk false
insertSync false
lsbOrderedFirst false
masterSPI true
numberOfSlaves 1
syncRegDepth 2
targetClockRate 6000000
targetSlaveSelectToSClkDelay 0.0
avalonSpec 2.0
inputClockRate 10000000
actualClockRate 5000000.0
actualSlaveSelectToSClkDelay 0.0
legacySignalsAllow false
slaveDataBusWidth 16
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CLOCKMULT 1
CLOCKPHASE 0
CLOCKPOLARITY 0
CLOCKUNITS "Hz"
DATABITS 8
DATAWIDTH 16
DELAYMULT "1.0E-9"
DELAYUNITS "ns"
EXTRADELAY 0
INSERT_SYNC 0
ISMASTER 1
LSBFIRST 0
NUMSLAVES 1
PREFIX "spi_"
SYNC_REG_DEPTH 2
TARGETCLOCK 6000000u
TARGETSSDELAY "0.0"

clk_in

clock_source v15.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

g_sensor_i2c_scl

altera_avalon_pio v15.1
mm_clock_crossing_bridge_0 m0   g_sensor_i2c_scl
  s1
system_pll c3  
  clk
clk_in clk_reset  
  reset
nios2_gen2 debug_reset_request  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
clockRate 10000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 10000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

g_sensor_i2c_sda

altera_avalon_pio v15.1
mm_clock_crossing_bridge_0 m0   g_sensor_i2c_sda
  s1
system_pll c3  
  clk
clk_in clk_reset  
  reset
nios2_gen2 debug_reset_request  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
clockRate 10000000
derived_has_tri true
derived_has_out false
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 10000000
HAS_IN 0
HAS_OUT 0
HAS_TRI 1
IRQ_TYPE NONE
RESET_VALUE 0

g_sensor_int

altera_avalon_pio v15.1
mm_clock_crossing_bridge_0 m0   g_sensor_int
  s1
system_pll c3  
  clk
nios2_gen2 irq  
  irq
debug_reset_request  
  reset
clk_in clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
direction Input
edgeType RISING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 2
clockRate 10000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture true
derived_edge_type RISING
derived_irq_type EDGE
derived_has_irq true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE RISING
FREQ 10000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

jtag_uart

altera_avalon_jtag_uart v15.1
nios2_gen2 data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
debug_reset_request  
  reset
system_pll c0  
  clk
clk_in clk_reset  
  reset


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions NO_INTERACTIVE_WINDOWS
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
clkFreq 120000000
avalonSpec 2.0
legacySignalAllow false
enableInteractiveInput false
enableInteractiveOutput false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

mm_clock_crossing_bridge_0

altera_avalon_mm_clock_crossing_bridge v15.1
nios2_gen2 data_master   mm_clock_crossing_bridge_0
  s0
debug_reset_request  
  m0_reset
debug_reset_request  
  s0_reset
system_pll c0  
  s0_clk
c3  
  m0_clk
clk_in clk_reset  
  m0_reset
clk_reset  
  s0_reset
m0   SEG7
  avalon_slave
m0   sysid_qsys
  control_slave
m0   pio_led
  s1
m0   pio_sw
  s1
m0   pio_key
  s1
m0   timer
  s1
m0   g_sensor_i2c_scl
  s1
m0   g_sensor_i2c_sda
  s1
m0   g_sensor_int
  s1


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
SYSINFO_ADDR_WIDTH 8
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 8
HDL_ADDR_WIDTH 10
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
COMMAND_FIFO_DEPTH 8
RESPONSE_FIFO_DEPTH 8
MASTER_SYNC_DEPTH 2
SLAVE_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_M0_CLK_CLOCK_RATE 10000000
AUTO_S0_CLK_CLOCK_RATE 120000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

modular_adc

altera_modular_adc v15.1
nios2_gen2 data_master   modular_adc
  sample_store_csr
data_master  
  sequencer_csr
debug_reset_request  
  reset_sink
system_pll c0  
  clock
c2  
  adc_pll_clock
locked_conduit  
  adc_pll_locked
clk_in clk_reset  
  reset_sink


Parameters

CORE_VAR 0
ENABLE_DEBUG 0
MONITOR_COUNT_WIDTH 12
CLOCK_FREQ 120000000
FAMILY MAX10FPGA
DEVICE_PART 10M50DAF484C6G
device_partname_fivechar_prefix 10M50
device_adc_type 33
max_adc_count_on_die 2
adc_count_on_device 2
device_power_supply_type 2
ip_is_for_which_adc 1
is_this_first_or_second_adc 1
analog_input_pin_mask 0
hard_pwd 0
clkdiv 2
tsclkdiv 1
tsclksel 1
refsel 0
external_vref 2.5
int_vref_vr 3.0
int_vref_nonvr 2.5
reference_voltage 2.5
prescalar 0
use_tsd true
en_tsd_max false
tsd_max 125
en_tsd_min false
tsd_min 0
use_ch0 false
en_thmax_ch0 false
thmax_ch0 0.0
en_thmin_ch0 false
thmin_ch0 0.0
use_ch1 true
en_thmax_ch1 false
thmax_ch1 0.0
en_thmin_ch1 false
thmin_ch1 0.0
use_ch2 true
en_thmax_ch2 false
thmax_ch2 0.0
en_thmin_ch2 false
thmin_ch2 0.0
use_ch3 true
en_thmax_ch3 false
thmax_ch3 0.0
en_thmin_ch3 false
thmin_ch3 0.0
use_ch4 true
en_thmax_ch4 false
thmax_ch4 0.0
en_thmin_ch4 false
thmin_ch4 0.0
use_ch5 true
en_thmax_ch5 false
thmax_ch5 0.0
en_thmin_ch5 false
thmin_ch5 0.0
use_ch6 true
en_thmax_ch6 false
thmax_ch6 0.0
en_thmin_ch6 false
thmin_ch6 0.0
use_ch7 true
en_thmax_ch7 false
thmax_ch7 0.0
en_thmin_ch7 false
thmin_ch7 0.0
use_ch8 true
prescaler_ch8 false
en_thmax_ch8 false
thmax_ch8 0.0
en_thmin_ch8 false
thmin_ch8 0.0
use_ch9 false
en_thmax_ch9 false
thmax_ch9 0.0
en_thmin_ch9 false
thmin_ch9 0.0
use_ch10 false
en_thmax_ch10 false
thmax_ch10 0.0
en_thmin_ch10 false
thmin_ch10 0.0
use_ch11 false
en_thmax_ch11 false
thmax_ch11 0.0
en_thmin_ch11 false
thmin_ch11 0.0
use_ch12 false
en_thmax_ch12 false
thmax_ch12 0.0
en_thmin_ch12 false
thmin_ch12 0.0
use_ch13 false
en_thmax_ch13 false
thmax_ch13 0.0
en_thmin_ch13 false
thmin_ch13 0.0
use_ch14 false
en_thmax_ch14 false
thmax_ch14 0.0
en_thmin_ch14 false
thmin_ch14 0.0
use_ch15 false
en_thmax_ch15 false
thmax_ch15 0.0
en_thmin_ch15 false
thmin_ch15 0.0
use_ch16 false
prescaler_ch16 false
en_thmax_ch16 false
thmax_ch16 0.0
en_thmin_ch16 false
thmin_ch16 0.0
seq_order_length 9
seq_order_slot_1 1
seq_order_slot_2 2
seq_order_slot_3 3
seq_order_slot_4 4
seq_order_slot_5 5
seq_order_slot_6 6
seq_order_slot_7 7
seq_order_slot_8 8
seq_order_slot_9 17
seq_order_slot_10 30
seq_order_slot_11 30
seq_order_slot_12 30
seq_order_slot_13 30
seq_order_slot_14 30
seq_order_slot_15 30
seq_order_slot_16 30
seq_order_slot_17 30
seq_order_slot_18 30
seq_order_slot_19 30
seq_order_slot_20 30
seq_order_slot_21 30
seq_order_slot_22 30
seq_order_slot_23 30
seq_order_slot_24 30
seq_order_slot_25 30
seq_order_slot_26 30
seq_order_slot_27 30
seq_order_slot_28 30
seq_order_slot_29 30
seq_order_slot_30 30
seq_order_slot_31 30
seq_order_slot_32 30
seq_order_slot_33 30
seq_order_slot_34 30
seq_order_slot_35 30
seq_order_slot_36 30
seq_order_slot_37 30
seq_order_slot_38 30
seq_order_slot_39 30
seq_order_slot_40 30
seq_order_slot_41 30
seq_order_slot_42 30
seq_order_slot_43 30
seq_order_slot_44 30
seq_order_slot_45 30
seq_order_slot_46 30
seq_order_slot_47 30
seq_order_slot_48 30
seq_order_slot_49 30
seq_order_slot_50 30
seq_order_slot_51 30
seq_order_slot_52 30
seq_order_slot_53 30
seq_order_slot_54 30
seq_order_slot_55 30
seq_order_slot_56 30
seq_order_slot_57 30
seq_order_slot_58 30
seq_order_slot_59 30
seq_order_slot_60 30
seq_order_slot_61 30
seq_order_slot_62 30
seq_order_slot_63 30
seq_order_slot_64 30
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CORE_VARIANT 0
CSD_LENGTH 9
CSD_SLOT_0 CH1
CSD_SLOT_1 CH2
CSD_SLOT_10 CH0
CSD_SLOT_11 CH0
CSD_SLOT_12 CH0
CSD_SLOT_13 CH0
CSD_SLOT_14 CH0
CSD_SLOT_15 CH0
CSD_SLOT_16 CH0
CSD_SLOT_17 CH0
CSD_SLOT_18 CH0
CSD_SLOT_19 CH0
CSD_SLOT_2 CH3
CSD_SLOT_20 CH0
CSD_SLOT_21 CH0
CSD_SLOT_22 CH0
CSD_SLOT_23 CH0
CSD_SLOT_24 CH0
CSD_SLOT_25 CH0
CSD_SLOT_26 CH0
CSD_SLOT_27 CH0
CSD_SLOT_28 CH0
CSD_SLOT_29 CH0
CSD_SLOT_3 CH4
CSD_SLOT_30 CH0
CSD_SLOT_31 CH0
CSD_SLOT_32 CH0
CSD_SLOT_33 CH0
CSD_SLOT_34 CH0
CSD_SLOT_35 CH0
CSD_SLOT_36 CH0
CSD_SLOT_37 CH0
CSD_SLOT_38 CH0
CSD_SLOT_39 CH0
CSD_SLOT_4 CH5
CSD_SLOT_40 CH0
CSD_SLOT_41 CH0
CSD_SLOT_42 CH0
CSD_SLOT_43 CH0
CSD_SLOT_44 CH0
CSD_SLOT_45 CH0
CSD_SLOT_46 CH0
CSD_SLOT_47 CH0
CSD_SLOT_48 CH0
CSD_SLOT_49 CH0
CSD_SLOT_5 CH6
CSD_SLOT_50 CH0
CSD_SLOT_51 CH0
CSD_SLOT_52 CH0
CSD_SLOT_53 CH0
CSD_SLOT_54 CH0
CSD_SLOT_55 CH0
CSD_SLOT_56 CH0
CSD_SLOT_57 CH0
CSD_SLOT_58 CH0
CSD_SLOT_59 CH0
CSD_SLOT_6 CH7
CSD_SLOT_60 CH0
CSD_SLOT_61 CH0
CSD_SLOT_62 CH0
CSD_SLOT_63 CH0
CSD_SLOT_7 CH8
CSD_SLOT_8 TSD
CSD_SLOT_9 CH0
DUAL_ADC_MODE false
IS_THIS_FIRST_OR_SECOND_ADC 1
PRESCALER_CH16 0
PRESCALER_CH8 0
REFSEL External VREF
USE_CH0 0
USE_CH1 1
USE_CH10 0
USE_CH11 0
USE_CH12 0
USE_CH13 0
USE_CH14 0
USE_CH15 0
USE_CH16 0
USE_CH2 1
USE_CH3 1
USE_CH4 1
USE_CH5 1
USE_CH6 1
USE_CH7 1
USE_CH8 1
USE_CH9 0
USE_TSD 1
VREF 2.5

nios2_gen2

altera_nios2_gen2 v15.1
system_pll c0   nios2_gen2
  clk
clk_in clk_reset  
  reset
data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
debug_reset_request  
  reset
data_master   alt_vip_vfr
  avalon_slave
irq  
  interrupt_sender
debug_reset_request  
  clock_master_reset
debug_reset_request  
  clock_reset_reset
data_master   system_pll
  pll_slave
debug_reset_request  
  inclk_interface_reset
data_master   mm_clock_crossing_bridge_0
  s0
debug_reset_request  
  m0_reset
debug_reset_request  
  s0_reset
data_master   onchip_memory
  s1
instruction_master  
  s1
debug_reset_request  
  reset1
data_master   sdram
  s1
instruction_master  
  s1
debug_reset_request  
  reset
data_master   arduino_pio
  s1
debug_reset_request  
  reset
data_master   tft_spi_dc
  s1
debug_reset_request  
  reset
data_master   modular_adc
  sample_store_csr
data_master  
  sequencer_csr
debug_reset_request  
  reset_sink
data_master   arduino_spi
  spi_control_port
debug_reset_request  
  reset
irq   timer
  irq
debug_reset_request  
  reset
irq   g_sensor_int
  irq
debug_reset_request  
  reset
debug_reset_request   alt_vip_itc
  is_clk_rst_reset
debug_reset_request   sysid_qsys
  reset
debug_reset_request   pio_led
  reset
debug_reset_request   pio_sw
  reset
debug_reset_request   pio_key
  reset
debug_reset_request   alt_vip_cpr_0
  reset
debug_reset_request   g_sensor_i2c_scl
  reset
debug_reset_request   g_sensor_i2c_sda
  reset


Parameters

tmr_enabled false
setting_disable_tmr_inj false
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_preciseIllegalMemAccessException false
setting_exportPCB false
setting_exportdebuginfo false
setting_clearXBitsLDNonBypass true
setting_bigEndian false
setting_export_large_RAMs false
setting_asic_enabled false
setting_asic_synopsys_translate_on_off false
setting_asic_third_party_synthesis false
setting_asic_add_scan_mode_input false
setting_oci_version 1
setting_fast_register_read false
setting_exportHostDebugPort false
setting_oci_export_jtag_signals false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
io_regionbase 0
io_regionsize 0
setting_support31bitdcachebypass true
setting_activateTrace false
setting_allow_break_inst false
setting_activateTestEndChecker false
setting_ecc_sim_test_ports false
setting_disableocitrace false
setting_activateMonitors true
setting_HDLSimCachesCleared true
setting_HBreakTest false
setting_breakslaveoveride false
mpu_useLimit false
mpu_enabled false
mmu_enabled false
mmu_autoAssignTlbPtrSz true
cpuReset false
resetrequest_enabled true
setting_removeRAMinit false
setting_shadowRegisterSets 0
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mmu_TLBMissExcOffset 0
resetOffset 0
exceptionOffset 32
cpuID 0
breakOffset 32
userDefinedSettings
tracefilename
resetSlave onchip_memory.s1
mmu_TLBMissExcSlave None
exceptionSlave onchip_memory.s1
breakSlave None
setting_interruptControllerType Internal
setting_branchpredictiontype Dynamic
setting_bhtPtrSz 8
cpuArchRev 1
stratix_dspblock_shift_mul false
shifterType fast_le_shift
multiplierType mul_fast32
mul_shift_choice 0
mul_32_impl 2
mul_64_impl 0
shift_rot_impl 1
dividerType no_div
mpu_minInstRegionSize 12
mpu_minDataRegionSize 12
mmu_uitlbNumEntries 4
mmu_udtlbNumEntries 6
mmu_tlbPtrSz 7
mmu_tlbNumWays 16
mmu_processIDNumBits 8
impl Fast
icache_size 4096
fa_cache_line 2
fa_cache_linesize 0
icache_tagramBlockType Automatic
icache_ramBlockType Automatic
icache_numTCIM 0
icache_burstType None
dcache_bursts false
dcache_victim_buf_impl ram
dcache_size 2048
dcache_tagramBlockType Automatic
dcache_ramBlockType Automatic
dcache_numTCDM 0
setting_exportvectors false
setting_usedesignware false
setting_ecc_present false
setting_ic_ecc_present true
setting_rf_ecc_present true
setting_mmu_ecc_present true
setting_dc_ecc_present true
setting_itcm_ecc_present true
setting_dtcm_ecc_present true
regfile_ramBlockType Automatic
ocimem_ramBlockType Automatic
ocimem_ramInit false
mmu_ramBlockType Automatic
bht_ramBlockType Automatic
cdx_enabled false
mpx_enabled false
debug_enabled true
debug_triggerArming true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_jtagInstanceID 0
debug_OCIOnchipTrace _128
debug_hwbreakpoint 0
debug_datatrigger 0
debug_traceType none
debug_traceStorage onchip_trace
master_addr_map false
instruction_master_paddr_base 0
instruction_master_paddr_size 0
flash_instruction_master_paddr_base 0
flash_instruction_master_paddr_size 0
data_master_paddr_base 0
data_master_paddr_size 0
tightly_coupled_instruction_master_0_paddr_base 0
tightly_coupled_instruction_master_0_paddr_size 0
tightly_coupled_instruction_master_1_paddr_base 0
tightly_coupled_instruction_master_1_paddr_size 0
tightly_coupled_instruction_master_2_paddr_base 0
tightly_coupled_instruction_master_2_paddr_size 0
tightly_coupled_instruction_master_3_paddr_base 0
tightly_coupled_instruction_master_3_paddr_size 0
tightly_coupled_data_master_0_paddr_base 0
tightly_coupled_data_master_0_paddr_size 0
tightly_coupled_data_master_1_paddr_base 0
tightly_coupled_data_master_1_paddr_size 0
tightly_coupled_data_master_2_paddr_base 0
tightly_coupled_data_master_2_paddr_size 0
tightly_coupled_data_master_3_paddr_base 0
tightly_coupled_data_master_3_paddr_size 0
instruction_master_high_performance_paddr_base 0
instruction_master_high_performance_paddr_size 0
data_master_high_performance_paddr_base 0
data_master_high_performance_paddr_size 0
resetAbsoluteAddr 151257088
exceptionAbsoluteAddr 151257120
breakAbsoluteAddr 151521312
mmu_TLBMissExcAbsAddr 0
dcache_bursts_derived false
dcache_size_derived 2048
breakSlave_derived nios2_gen2.debug_mem_slave
dcache_lineSize_derived 32
setting_ioregionBypassDCache false
setting_bit31BypassDCache true
translate_on "synthesis translate_on"
translate_off "synthesis translate_off"
debug_onchiptrace false
debug_offchiptrace false
debug_insttrace false
debug_datatrace false
instAddrWidth 28
faAddrWidth 1
dataAddrWidth 28
tightlyCoupledDataMaster0AddrWidth 1
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster3AddrWidth 1
dataMasterHighPerformanceAddrWidth 1
instructionMasterHighPerformanceAddrWidth 1
instSlaveMapParam <address-map><slave name='sdram.s1' start='0x4000000' end='0x8000000' type='altera_avalon_new_sdram_controller.s1' /><slave name='onchip_memory.s1' start='0x9040000' end='0x9060F58' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x9080800' end='0x9081000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>
faSlaveMapParam
dataSlaveMapParam <address-map><slave name='sdram.s1' start='0x4000000' end='0x8000000' type='altera_avalon_new_sdram_controller.s1' /><slave name='timer.s1' start='0x8000000' end='0x8000020' type='altera_avalon_timer.s1' /><slave name='SEG7.avalon_slave' start='0x8000020' end='0x8000040' type='SEG7_IF.avalon_slave' /><slave name='g_sensor_int.s1' start='0x8000040' end='0x8000050' type='altera_avalon_pio.s1' /><slave name='g_sensor_i2c_sda.s1' start='0x8000050' end='0x8000060' type='altera_avalon_pio.s1' /><slave name='g_sensor_i2c_scl.s1' start='0x8000060' end='0x8000070' type='altera_avalon_pio.s1' /><slave name='pio_key.s1' start='0x8000070' end='0x8000080' type='altera_avalon_pio.s1' /><slave name='pio_sw.s1' start='0x8000080' end='0x8000090' type='altera_avalon_pio.s1' /><slave name='pio_led.s1' start='0x8000090' end='0x80000A0' type='altera_avalon_pio.s1' /><slave name='sysid_qsys.control_slave' start='0x80000A0' end='0x80000A8' type='altera_avalon_sysid_qsys.control_slave' /><slave name='onchip_memory.s1' start='0x9040000' end='0x9060F58' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x9080800' end='0x9081000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='modular_adc.sample_store_csr' start='0x9081000' end='0x9081200' type='altera_modular_adc.sample_store_csr' /><slave name='alt_vip_vfr.avalon_slave' start='0x9081200' end='0x9081280' type='alt_vip_vfr.avalon_slave' /><slave name='arduino_spi.spi_control_port' start='0x9081280' end='0x90812A0' type='altera_avalon_spi.spi_control_port' /><slave name='tft_spi_dc.s1' start='0x90812A0' end='0x90812B0' type='altera_avalon_pio.s1' /><slave name='arduino_pio.s1' start='0x90812B0' end='0x90812C0' type='altera_avalon_pio.s1' /><slave name='system_pll.pll_slave' start='0x90812C0' end='0x90812D0' type='altpll.pll_slave' /><slave name='modular_adc.sequencer_csr' start='0x90812D0' end='0x90812D8' type='altera_modular_adc.sequencer_csr' /><slave name='jtag_uart.avalon_jtag_slave' start='0x90812D8' end='0x90812E0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
dataMasterHighPerformanceMapParam
instructionMasterHighPerformanceMapParam
clockFrequency 120000000
deviceFamilyName MAX10FPGA
internalIrqMaskSystemInfo 15
customInstSlavesSystemInfo <info/>
customInstSlavesSystemInfo_nios_a <info/>
customInstSlavesSystemInfo_nios_b <info/>
customInstSlavesSystemInfo_nios_c <info/>
deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
AUTO_DEVICE 10M50DAF484C6G
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CLK_CLOCK_DOMAIN 6
AUTO_CLK_RESET_DOMAIN 6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x09080820
CPU_ARCH_NIOS2_R1
CPU_FREQ 120000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 28
DCACHE_BYPASS_MASK 0x80000000
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
EXCEPTION_ADDR 0x09040020
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_EXTRA_EXCEPTION_INFO
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
INITDA_SUPPORTED
INST_ADDR_WIDTH 28
NUM_OF_SHADOW_REG_SETS 0
OCI_VERSION 1
RESET_ADDR 0x09040000

onchip_memory

altera_avalon_onchip_memory2 v15.1
nios2_gen2 data_master   onchip_memory
  s1
instruction_master  
  s1
debug_reset_request  
  reset1
system_pll c0  
  clk1
clk_in clk_reset  
  reset1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName onchip_mem.hex
instanceID NONE
memorySize 135000
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
copyInitFile false
useShallowMemBlocks false
writable true
ecc_enabled false
resetrequest_enabled true
autoInitializationFileName de10_lite_qsys_onchip_memory
deviceFamily MAX10FPGA
deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width 16
derived_set_data_width 32
derived_gui_ram_block_type Automatic
derived_is_hardcopy false
derived_init_file_name de10_lite_qsys_onchip_memory.hex
generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE de10_lite_qsys_onchip_memory
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 135000
WRITABLE 1

pio_key

altera_avalon_pio v15.1
mm_clock_crossing_bridge_0 m0   pio_key
  s1
system_pll c3  
  clk
clk_in clk_reset  
  reset
nios2_gen2 debug_reset_request  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 2
clockRate 10000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 10000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led

altera_avalon_pio v15.1
mm_clock_crossing_bridge_0 m0   pio_led
  s1
system_pll c3  
  clk
clk_in clk_reset  
  reset
nios2_gen2 debug_reset_request  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 10
clockRate 10000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 10
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 10000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_sw

altera_avalon_pio v15.1
mm_clock_crossing_bridge_0 m0   pio_sw
  s1
system_pll c3  
  clk
clk_in clk_reset  
  reset
nios2_gen2 debug_reset_request  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 10
clockRate 10000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 10
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 10000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

sdram

altera_avalon_new_sdram_controller v15.1
alt_vip_vfr avalon_master   sdram
  s1
nios2_gen2 data_master  
  s1
instruction_master  
  s1
debug_reset_request  
  reset
system_pll c0  
  clk
clk_in clk_reset  
  reset


Parameters

TAC 5.4
TRCD 15.0
TRFC 70.0
TRP 15.0
TWR 14.0
casLatency 3
columnWidth 10
dataWidth 16
generateSimulationModel false
initRefreshCommands 2
model single_Micron_MT48LC4M32B2_7_chip
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 7.8125
rowWidth 13
masteredTristateBridgeSlave 0
TMRD 3
initNOPDelay 0.0
registerDataIn true
clockRate 120000000
componentName de10_lite_qsys_sdram
size 67108864
addressWidth 25
bankWidth 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CAS_LATENCY 3
CONTENTS_INFO
INIT_NOP_DELAY 0.0
INIT_REFRESH_COMMANDS 2
IS_INITIALIZED 1
POWERUP_DELAY 100.0
REFRESH_PERIOD 7.8125
REGISTER_DATA_IN 1
SDRAM_ADDR_WIDTH 25
SDRAM_BANK_WIDTH 2
SDRAM_COL_WIDTH 10
SDRAM_DATA_WIDTH 16
SDRAM_NUM_BANKS 4
SDRAM_NUM_CHIPSELECTS 1
SDRAM_ROW_WIDTH 13
SHARED_DATA 0
SIM_MODEL_BASE 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
T_AC 5.4
T_MRD 3
T_RCD 15.0
T_RFC 70.0
T_RP 15.0
T_WR 14.0

sysid_qsys

altera_avalon_sysid_qsys v15.1
mm_clock_crossing_bridge_0 m0   sysid_qsys
  control_slave
system_pll c3  
  clk
clk_in clk_reset  
  reset
nios2_gen2 debug_reset_request  
  reset


Parameters

id 0
timestamp 1471318310
AUTO_DEVICE_FAMILY MAX10FPGA
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 1471318310

system_pll

altpll v15.1
nios2_gen2 data_master   system_pll
  pll_slave
debug_reset_request  
  inclk_interface_reset
clk_in clk  
  inclk_interface
clk_reset  
  inclk_interface_reset
c0   nios2_gen2
  clk
c0   sdram
  clk
c0   jtag_uart
  clk
c0   onchip_memory
  clk1
c0   modular_adc
  clock
c2  
  adc_pll_clock
locked_conduit  
  adc_pll_locked
c0   alt_vip_cpr_0
  clock
c0   alt_vip_vfr
  clock_master
c0  
  clock_reset
c0   alt_vip_itc
  is_clk_rst
c0   mm_clock_crossing_bridge_0
  s0_clk
c3  
  m0_clk
c3   pio_led
  clk
c3   pio_sw
  clk
c3   pio_key
  clk
c3   timer
  clk
c3   sysid_qsys
  clk
c3   arduino_pio
  clk
c3   tft_spi_dc
  clk
c3   arduino_spi
  clk
c3   g_sensor_int
  clk
c3   g_sensor_i2c_sda
  clk
c3   g_sensor_i2c_scl
  clk
c3   SEG7
  clock_sink


Parameters

HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY MAX 10
WIDTH_CLOCK 5
WIDTH_PHASECOUNTERSELECT
PRIMARY_CLOCK
INCLK0_INPUT_FREQUENCY 100000
INCLK1_INPUT_FREQUENCY
OPERATION_MODE NORMAL
PLL_TYPE AUTO
QUALIFY_CONF_DONE
COMPENSATE_CLOCK CLK0
SCAN_CHAIN
GATE_LOCK_SIGNAL
GATE_LOCK_COUNTER
LOCK_HIGH
LOCK_LOW
VALID_LOCK_MULTIPLIER
INVALID_LOCK_MULTIPLIER
SWITCH_OVER_ON_LOSSCLK
SWITCH_OVER_ON_GATED_LOCK
ENABLE_SWITCH_OVER_COUNTER
SKIP_VCO
SWITCH_OVER_COUNTER
SWITCH_OVER_TYPE
FEEDBACK_SOURCE
BANDWIDTH
BANDWIDTH_TYPE AUTO
SPREAD_FREQUENCY
DOWN_SPREAD
SELF_RESET_ON_GATED_LOSS_LOCK
SELF_RESET_ON_LOSS_LOCK
CLK0_MULTIPLY_BY 12
CLK1_MULTIPLY_BY 12
CLK2_MULTIPLY_BY 1
CLK3_MULTIPLY_BY 1
CLK4_MULTIPLY_BY 4
CLK5_MULTIPLY_BY
CLK6_MULTIPLY_BY
CLK7_MULTIPLY_BY
CLK8_MULTIPLY_BY
CLK9_MULTIPLY_BY
EXTCLK0_MULTIPLY_BY
EXTCLK1_MULTIPLY_BY
EXTCLK2_MULTIPLY_BY
EXTCLK3_MULTIPLY_BY
CLK0_DIVIDE_BY 1
CLK1_DIVIDE_BY 1
CLK2_DIVIDE_BY 1
CLK3_DIVIDE_BY 1
CLK4_DIVIDE_BY 1
CLK5_DIVIDE_BY
CLK6_DIVIDE_BY
CLK7_DIVIDE_BY
CLK8_DIVIDE_BY
CLK9_DIVIDE_BY
EXTCLK0_DIVIDE_BY
EXTCLK1_DIVIDE_BY
EXTCLK2_DIVIDE_BY
EXTCLK3_DIVIDE_BY
CLK0_PHASE_SHIFT 0
CLK1_PHASE_SHIFT -3000
CLK2_PHASE_SHIFT 0
CLK3_PHASE_SHIFT 0
CLK4_PHASE_SHIFT 0
CLK5_PHASE_SHIFT
CLK6_PHASE_SHIFT
CLK7_PHASE_SHIFT
CLK8_PHASE_SHIFT
CLK9_PHASE_SHIFT
EXTCLK0_PHASE_SHIFT
EXTCLK1_PHASE_SHIFT
EXTCLK2_PHASE_SHIFT
EXTCLK3_PHASE_SHIFT
CLK0_DUTY_CYCLE 50
CLK1_DUTY_CYCLE 50
CLK2_DUTY_CYCLE 50
CLK3_DUTY_CYCLE 50
CLK4_DUTY_CYCLE 50
CLK5_DUTY_CYCLE
CLK6_DUTY_CYCLE
CLK7_DUTY_CYCLE
CLK8_DUTY_CYCLE
CLK9_DUTY_CYCLE
EXTCLK0_DUTY_CYCLE
EXTCLK1_DUTY_CYCLE
EXTCLK2_DUTY_CYCLE
EXTCLK3_DUTY_CYCLE
PORT_clkena0 PORT_UNUSED
PORT_clkena1 PORT_UNUSED
PORT_clkena2 PORT_UNUSED
PORT_clkena3 PORT_UNUSED
PORT_clkena4 PORT_UNUSED
PORT_clkena5 PORT_UNUSED
PORT_extclkena0
PORT_extclkena1
PORT_extclkena2
PORT_extclkena3
PORT_extclk0 PORT_UNUSED
PORT_extclk1 PORT_UNUSED
PORT_extclk2 PORT_UNUSED
PORT_extclk3 PORT_UNUSED
PORT_CLKBAD0 PORT_UNUSED
PORT_CLKBAD1 PORT_UNUSED
PORT_clk0 PORT_USED
PORT_clk1 PORT_USED
PORT_clk2 PORT_USED
PORT_clk3 PORT_USED
PORT_clk4 PORT_USED
PORT_clk5 PORT_UNUSED
PORT_clk6
PORT_clk7
PORT_clk8
PORT_clk9
PORT_SCANDATA PORT_UNUSED
PORT_SCANDATAOUT PORT_UNUSED
PORT_SCANDONE PORT_UNUSED
PORT_SCLKOUT1
PORT_SCLKOUT0
PORT_ACTIVECLOCK PORT_UNUSED
PORT_CLKLOSS PORT_UNUSED
PORT_INCLK1 PORT_UNUSED
PORT_INCLK0 PORT_USED
PORT_FBIN PORT_UNUSED
PORT_PLLENA PORT_UNUSED
PORT_CLKSWITCH PORT_UNUSED
PORT_ARESET PORT_UNUSED
PORT_PFDENA PORT_UNUSED
PORT_SCANCLK PORT_UNUSED
PORT_SCANACLR PORT_UNUSED
PORT_SCANREAD PORT_UNUSED
PORT_SCANWRITE PORT_UNUSED
PORT_ENABLE0
PORT_ENABLE1
PORT_LOCKED PORT_UNUSED
PORT_CONFIGUPDATE PORT_UNUSED
PORT_FBOUT
PORT_PHASEDONE PORT_UNUSED
PORT_PHASESTEP PORT_UNUSED
PORT_PHASEUPDOWN PORT_UNUSED
PORT_SCANCLKENA PORT_UNUSED
PORT_PHASECOUNTERSELECT PORT_UNUSED
PORT_VCOOVERRANGE
PORT_VCOUNDERRANGE
DPA_MULTIPLY_BY
DPA_DIVIDE_BY
DPA_DIVIDER
VCO_MULTIPLY_BY
VCO_DIVIDE_BY
SCLKOUT0_PHASE_SHIFT
SCLKOUT1_PHASE_SHIFT
VCO_FREQUENCY_CONTROL
VCO_PHASE_SHIFT_STEP
USING_FBMIMICBIDIR_PORT
SCAN_CHAIN_MIF_FILE
AVALON_USE_SEPARATE_SYSCLK NO
HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 1 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 12 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 1 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 1 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 4 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 12 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 100000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -3000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 1 CT#PORT_LOCKED PORT_UNUSED
HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 10.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 40.00000000 PT#OUTPUT_FREQ3 10.00000000 PT#OUTPUT_FREQ2 10.00000000 PT#OUTPUT_FREQ1 120.00000000 PT#OUTPUT_FREQ0 120.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 -3.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 40.000000 PT#EFF_OUTPUT_FREQ_VALUE3 10.000000 PT#EFF_OUTPUT_FREQ_VALUE2 10.000000 PT#EFF_OUTPUT_FREQ_VALUE1 120.000000 PT#EFF_OUTPUT_FREQ_VALUE0 120.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1465289779416238.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}
HIDDEN_IS_FIRST_EDIT 0
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

tft_spi_dc

altera_avalon_pio v15.1
nios2_gen2 data_master   tft_spi_dc
  s1
debug_reset_request  
  reset
system_pll c3  
  clk
clk_in clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
clockRate 10000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 10000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

timer

altera_avalon_timer v15.1
mm_clock_crossing_bridge_0 m0   timer
  s1
system_pll c3  
  clk
nios2_gen2 irq  
  irq
debug_reset_request  
  reset
clk_in clk_reset  
  reset


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 10000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 9999
mult 0.001
ticksPerSec 1000.0
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 10000000
LOAD_VALUE 9999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
generation took 0.00 seconds rendering took 0.10 seconds